In semiconductor processing, SOI technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g. Si, overlays a layer of insulating material (buried oxide region). This relatively thin layer of semiconducting material is generally the area wherein active devices are formed in SOI devices. Devices formed on SOI offer many advantages over their bulk Si counterparts, including higher performance, absence of latch-up, higher packing density and low voltage applications.
Despite the advantages obtained using SOI technology, SOI circuits, like other electronic devices, are susceptible to electrostatic discharge (ESD), i.e. a surge in voltage (negative or positive) that occurs when a large amount of current is applied in the circuit. Moreover, the handling of SOI devices themselves may lead to charging of the substrate.
To discharge electrostatic impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diodes, do not work well on SOI because of the presence of the relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current drivability because the current is carried laterally (limited by the thickness of the semiconductor material).
One approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 4,989,057 to Lu. The Lu reference discloses a gated diode, which could be used for ESD design. The gate diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad. Although the diode disclosed in Lu can provide some ESD protection, the disclosed diode does not allow for obtaining ideal diode characteristics. Some reasons preventing ideal diode characteristics with the diodes disclosed in Lu include: (1) alignment tolerance of the substrate causes large process-induced variations; and (2) the conventional diode structure may be a polysilicon diode, which receives extensions and halo implants (implants normally utilized in deep sub-micron MOSFETS) that degrades the ideal characteristics on SOI.
Other ESD protection schemes for the front side of the SOI wafer are also known. Common to each is that the energy developed across prior art ESD protection schemes can be substantial. Thus, the heat generated by such ESD protection schemes must be dissipated by the relatively thin semiconducting layer. In cases wherein the heat becomes too excessive, destruction of the SOI circuit may occur.
In view of the above drawbacks with prior art ESD protection schemes, there is a need for developing new and improved ESD protection schemes that can be used for dissipating electrostatic charge from the substrate of an SOI wafer.